An apparatus of the kind mentioned above is already known from the U.S. Pat. No. 4,535,459. In this apparatus, there are included two series-connected D flip-flops, and the received data signal is applied to the data input of the first flip-flop. Two anti-phase clock signals are formed from the oscillator timing signal, one of the clock signals being taken to the clock input on one flip-flop and the other being taken to the clock input on the other flip-flop. There are thus obtained two differently delayed copies of the data signal on the outputs of the flip-flops. The data signal and the first delayed copy, which occur on the first flip-flop, are supplied to a first EXCLUSIVE-OR gate. There is thus formed a pulse train with pulse duration responsive to the phase position of the timing signal from the oscillator relative the phase position of the received data signal. Both delayed copies of the data signal occurring at the second flip-flop are supplied to a second EXCLUSIVE-OR gate. There is thus formed a pulse train with a pulse duration which is independent of the above-mentioned phase position. Both pulse trains are integrated, and a control signal to the oscillator is formed, this signal being responsive to the difference between the integrated pulse trains.